Accelerate EDA verification at lower cost

Improve productivity and economics of your design environment with tools running on HPE Apollo 70 System built on Marvell® ThunderX2® Armv8-A®processors

Today’s hardware designers are faced with numerous challenges as they are tasked with building increasingly complex systems that must meet stringent quality, cost and time-to-market requirements. One of the largest challenges — and a key issue as the industry moves to increasingly sophisticated designs — is device verification.

Device verification, making sure designs execute correctly and reliably, is a huge part of the process before designs go to tape-out. With advanced SoC designs having tens of millions of gates, high-performance computing (HPC) with vast amount of memory bandwidth is essential. Engineers must perform extensive computer simulations on large-scale server farms, iterating and refining designs as flaws are discovered and corrected. Along with verification of massive and highly complex designs, engineers are also faced with business pressures of shorter product cycles, more rigorous reliability requirements as devices become mission-critical and limited IT budgets.

In this paper, you will learn about how an ecosystem of companies is delivering a powerful, dense, cost-effective solution for EDA customers looking for more capable alternatives to existing server platforms. The Hewlett Packard Enterprise (HPE) Apollo 70 System, based on the Marvell ThunderX2 processor, is built to deliver high levels of performance, high core counts and high memory bandwidth for a variety of HPC requirements. In tandem with the Cadence Verification Suite, this solution is helping designers and engineers:

  • combat the challenges of increased design complexity and time to market pressures

  • improve the economics of chip design to enable faster innovation and create higher quality products

  • manage a variety of workloads and deliver high throughput as part of the verification process


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